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1. general description the 74abt543a high performance bicmos device combines low static and dynamic power dissipation with high speed and high output drive. the 74abt543a octal registered transceiver contains two sets of d-type latches for temporary storage of data ?owing in either direction. separate latch enable ( leab, leba) and output enable ( oeab, oeba) inputs are provided for each register to permit independent control of data transfer in either direction. the outputs are guaranteed to sink 64 ma. 2. features n combines 74abt245 and 74abt373 type functions in one device n 8-bit octal transceiver with d-type latch n back-to-back registers for storage n separate controls for data ?ow in each direction n live insertion and extraction permitted n output capability: +64 ma to - 32 ma n power-up 3-state n power-up reset n latch-up protection exceeds 500 ma per jesd78b class ii level a n esd protection: u hbm jesd22-a114f exceeds 2000 v u mm jesd22-a115-a exceeds 200 v 3. ordering information 74abt543a octal latched transceiver with dual enable; 3-state rev. 03 26 january 2010 product data sheet table 1. ordering information type number package temperature range name description version 74abt543ad - 40 cto+85 c so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1 74ABT543ADB - 40 cto+85 c ssop24 plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 74abt543apw - 40 cto+85 c tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 2 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state 4. functional diagram fig 1. logic symbol fig 2. iec logic symbol 001aae900 14 1 leab leba b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 22 21 20 19 18 17 16 15 345678910 23 2 13 eba oeba oeab 11 eab 001aae901 2 3 6d 5d 22 4 21 3 g1 2en4 (ab) 1c5 2 1 1en3 (ba) 13 g2 2c6 23 14 11 520 6 19 7 18 8 17 9 16 10 15 fig 3. logic diagram 001aae902 4 q a1 3 a0 d le detail a detail a 7 5 a2 6 a3 7 a4 8 a5 9 a6 10 a7 b1 b2 b3 b4 b5 b6 b7 21 b0 22 20 19 18 17 16 15 qd le 2 oeba 23 eba 1 leba oeab 13 eab 11 leab 14
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 3 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state 5. pinning information 5.1 pinning 5.2 pin description fig 4. pin con?guration leba v cc oeba eba a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 eab leab gnd oeab 001aae899 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 74abt543a table 2. pin description symbol pin description leba 1 b-to-a latch enable input (active low) oeba 2 b-to-a output enable input (active low) a0 to a7 3, 4, 5, 6, 7, 8, 9, 10 data input or output eab 11 a-to-b enable input (active low) gnd 12 ground (0 v) oeab 13 a-to-b output enable input (active low) leab 14 a-to-b latch enable input (active low) b0 to b7 22, 21, 20, 19, 18, 17, 16, 15 data input or output eba 23 b-to-a enable input (active low) v cc 24 positive supply voltage
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 4 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state 6. functional description 6.1 function table [1] h = high voltage level; h = high voltage level one set-up time prior to the low-to-high clock transition of lexx or exx (xx = ab or ba); l = low voltage level; l = low voltage level one set-up time prior to the low-to-high clock transition of lexx or exx (xx = ab or ba); - = low-to-high clock transition of lexx or exx (xx = ab or ba); nc = no change; x = dont care; z = high-impedance off-state. 6.2 description the 74abt543a contains two sets of eight d-type latches, with separate control pins for each set. using data ?ow from a-to-b as an example, when the a-to-b enable ( eab) input, the a-to-b latch enable ( leab) input and the a-to-b output enable ( oeab) input are all low, the a-to-b path is transparent. a subsequent low-to-high transition of the leab signal puts the a data into the latches where it is stored and the b outputs no longer change with the a inputs. with eab and oeab both low, the 3-state b output buffers are active and display the data present at the outputs of the a latches. control of data ?ow from b-to-a is similar, but using the eba, leba, and oeba inputs. table 3. function selection [1] input output status oexx exx lexx an or bn bn or an hxxxz disabled xhxxz l - l h z disabled + latch lz ll - h h latch + display ll l l l h h transparent ll l l h x nc hold
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 5 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 8. recommended operating conditions 9. static characteristics table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 0.5 +7.0 v v i input voltage [1] - 1.2 +7.0 v v o output voltage output in off-state or high-state [1] - 0.5 +5.5 v i ik input clamping current v i < 0 v - 18 - ma i ok output clamping current v o < 0 v - 50 - ma i o output current output in low-state - 128 ma t j junction temperature [2] - 150 c t stg storage temperature - 65 +150 c table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 4.5 - 5.5 v v i input voltage 0 - v cc v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i oh high-level output current - 32--ma i ol low-level output current - - 64 ma d t/ d v input transition rise and fall rate 0 - 10 ns/v t amb ambient temperature in free air - 40 - +85 c table 6. static characteristics symbol parameter conditions 25 c - 40 c to +85 c unit min typ max min max v ik input clamping voltage v cc = 4.5 v; i ik = - 18 ma - 1.2 - 0.9 - - 1.2 - v v oh high-level output voltage v i = v il or v ih v cc = 4.5 v; i oh = - 3 ma 2.5 3.2 - 2.5 - v v cc = 5.0 v; i oh = - 3 ma 3.0 3.7 - 3.0 - v v cc = 4.5 v; i oh = - 32 ma 2.0 2.3 - 2.0 - v v ol low-level output voltage v cc = 4.5 v; i ol = 64 ma; v i =v il or v ih - 0.3 0.55 - 0.55 v v ol(pu) power-up low-level output voltage v cc = 5.5 v; i o = 1 ma; v i = gnd or v cc - 0.13 0.55 - 0.55 v
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 6 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state [1] this parameter is valid for any v cc between 0 v and 2.1 v, with a transition time of up to 10 ms. from v cc = 2.1 v to v cc =5v 10 %, a transition time of up to 100 ms is permitted. [2] not more than one output should be tested at a time, and the duration of the test should not exceed one second. [3] this is the increase in supply current for each input at 3.4 v. 10. dynamic characteristics i i input leakage current v cc = 5.5 v; v i = gnd or 5.5 v oeab, oeba - 0.01 1.0 - 1.0 m a an, bn - 5.0 100 - 100 m a i off power-off leakage current v cc = 0.0 v; v i or v o 4.5 v - 5.0 100 - 100 m a i o(pu/pd) power-up/power-down output current v cc = 2.1 v; v o = 0.5 v; v i = gnd or v cc ; oeab, oeba dont care [1] - 5.0 50 - 50 m a i oz off-state output current v cc = 5.5 v; v i = v il or v ih v o = 2.7 v - 5.0 50 - 50 m a v o = 0.5 v - - 5.0 - 50 - - 50 m a i lo output leakage current high-state; v o = 5.5 v; v cc = 5.5 v; v i = gnd or v cc - 5.0 50 - 50 m a i o output current v cc = 5.5 v; v o = 2.5 v [2] - 180 - 65 - 40 - 180 - 40 ma i cc supply current v cc = 5.5 v; v i = gnd or v cc outputs high-state - 110 250 - 250 m a outputs low-state - 20 30 - 30 ma outputs disabled - 110 250 - 250 m a d i cc additional supply current per input pin; v cc = 5.5 v; one input pin at 3.4 v, other inputs at v cc or gnd [3] - 0.3 1.5 - 1.5 ma c i input capacitance v i = 0 v or v cc -4- - -pf c i/o input/output capacitance outputs disabled; v o = 0 v or v cc -7- - -pf table 6. static characteristics continued symbol parameter conditions 25 c - 40 c to +85 c unit min typ max min max table 7. dynamic characteristics gnd = 0 v; for test circuit, see figure 10 . symbol parameter conditions 25 c; v cc = 5.0 v - 40 c to +85 c; v cc = 5.0 v 0.5 v unit min typ max min max t plh low to high propagation delay an to bn or bn to an; see figure 5 1.0 2.9 4.5 1.0 5.2 ns leba to an or leab to bn; see figure 6 1.0 3.4 5.1 1.0 6.2 ns t phl high to low propagation delay an to bn or bn to an; see figure 5 1.9 3.6 5.2 1.9 5.7 ns leba to an or leab to bn; see figure 6 2.1 4.3 6.0 2.1 6.7 ns t pzh off-state to high propagation delay oeba to an, oeab to bn; see figure 7 1.0 3.2 5.1 1.0 6.2 ns eba to an, eab to bn; see figure 7 1.0 3.4 5.1 1.0 6.2 ns
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 7 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state 11. waveforms t pzl off-state to low propagation delay oeba to an, oeab to bn; see figure 8 2.0 4.3 5.9 2.0 6.6 ns eba to an, eab to bn; see figure 8 2.0 4.4 6.1 2.0 6.8 ns t phz high to off-state propagation delay oeba to an, oeab to bn; see figure 7 2.0 4.0 5.7 2.0 6.2 ns eba to an, eab to bn; see figure 7 2.0 3.6 5.4 2.0 5.9 ns t plz low to off-state propagation delay oeba to an, oeab to bn; see figure 8 1.0 3.0 4.6 1.0 5.0 ns eba to an, eab to bn; see figure 8 1.0 3.0 4.6 1.0 5.0 ns t su(h) set-up time high an to leab, bn to leba; see figure 9 2.5 1.0 - 2.5 - ns an to eab, bn to eba; see figure 9 3.5 1.3 - 3.5 - ns t su(l) set-up time low an to leab, bn to leba; see figure 9 3.0 1.4 - 3.0 - ns an to eab, bn to eba; see figure 9 3.0 1.4 - 3.0 - ns t h(h) hold time high leab to an, leba to bn; see figure 9 +0.5 - 0.8 - 0.5 - ns eab to an, eba to bn; see figure 9 +0.5 - 0.8 - 0.5 - ns t h(l) hold time low leab to an, leba to bn; see figure 9 +0.5 - 0.6 - 0.5 - ns eab to an, eba to bn; see figure 9 +0.5 - 0.6 - 0.5 - ns t wl pulse width low latch enable; see figure 9 3.5 1.0 - 3.5 - ns table 7. dynamic characteristics continued gnd = 0 v; for test circuit, see figure 10 . symbol parameter conditions 25 c; v cc = 5.0 v - 40 c to +85 c; v cc = 5.0 v 0.5 v unit min typ max min max v m = 1.5 v. v ol and v oh are typical voltage output levels that occur with the output load. fig 5. propagation delay input (an, bn) to output (bn, an) 001aae904 an or bn bn or an v m gnd v i v oh v ol v m t plh t phl v m v m
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 8 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state v m = 1.5 v. v ol and v oh are typical voltage output levels that occur with the output load. fig 6. propagation delay latch enable ( leab, leb a) to output (an, bn) 001aae903 an or bn v m v ol v oh gnd v i v m t phl t plh v m v m leab or leba v m = 1.5 v. v oh is a typical voltage output level that occurs with the output load. fig 7. propagation delay 3-state output enable to high-level and output disable from high-level 001aae907 v m v m v oh - 0.3 v v oh gnd v i gnd v m t phz t pzh an, bn oeab, oeba, eab, eba v m = 1.5 v. v ol is a typical voltage output level that occurs with the output load. fig 8. propagation delay 3-state output enable to low-level and output disable from low-level 001aae906 v m v m 3.5 v v ol + 0.3 v v m t plz t pzl an, bn oeab, oeba, eab, eba v ol v i gnd
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 9 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state v m = 1.5 v. the shaded areas indicate when the input is permitted to change for predictable output performance. fig 9. data set-up and hold times and latch enable pulse width 001aae905 v m an, bn leab, leba, eab, eba v m v m v m v m v m t su(h) t h(h) t su(l) t h(l) t wl v i gnd v i gnd a. input pulse de?nition b. test circuit test data is given in t ab le 8 . de?nitions test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = test voltage for switching times. fig 10. load circuitry for switching times 001aac221 v m v m t w t w 10 % 90 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % 10 % t f t r t r t f v ext v cc v i v o mna616 dut c l r t r l r l g table 8. test data input load v ext v i f i t w t r , t f c l r l t phl , t plh t pzh , t phz t pzl , t plz 3.0 v 1 mhz 500 ns 2.5 ns 50 pf 500 w open open 7.0 v
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 10 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state 12. package outline fig 11. package outline sot137-1 (so24) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 99-12-27 03-02-19
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 11 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state fig 12. package outline sot340-1 (ssop24) unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 0.8 0.4 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot340-1 mo-150 99-12-27 03-02-19 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 112 24 13 0.25 y pin 1 index 0 2.5 5 mm scale ssop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 a max. 2
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 12 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state fig 13. package outline sot355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 112 24 13 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 13 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state 13. abbreviations 14. revision history table 9. abbreviations acronym description bicmos bipolar complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model table 10. revision history document id release date data sheet status change notice supersedes 74abt543a_3 20100126 product data sheet - 74abt543a_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? dip 24 (sot222-1) package removed from section 3 order ing inf or mation and. section 12 p ac kage outline 74abt543a_2 19980924 product speci?cation - 74abt543a_1 74abt543a_1 19950419 product speci?cation - -
74abt543a_3 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 03 26 january 2010 14 of 15 nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors 74abt543a octal latched transceiver with dual enable; 3-state ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 26 january 2010 document identifier: 74abt543a_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 14 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 16 contact information. . . . . . . . . . . . . . . . . . . . . 14 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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